1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device for safely testing a characteristic of an input/output sense amplifier.
2. Description of the Related Art
An input/output sense amplifier (IOSA) converts a signal provided from a memory cell array into a high level signal suitable for outputting the signal to an external device.
The IOSA is a sensitive circuit block and markedly affects operational characteristics of the semiconductor memory device. Therefore, a characteristic test of the IOSA is essentially required when the semiconductor memory device is tested.
FIG. 1 is a timing diagram illustrating a relationship between a latch enable signal of an IOSA and output data in a conventional semiconductor memory device.
The IOSA is typically tested based on a latch enable signal having a first pulse shape generated by an auto pulse generator both in test mode and normal mode. FIG. 1 illustrates an example of the latch enable signal of the IOSA. The latch enable signal of FIG. 1 is in an enabled state during a valid data period, and has a second pulse shape. Therefore, the valid data is tested alone, and a test error occurs when the IOSA having the timing characteristic of FIG. 1 is tested. In the conventional IOSA, a delay time of the latch enable signal is increased or decreased, or a pulse duration of the latch enable signal is increased for testing output data of the IOSA during the valid data period.
Accordingly, a method of testing not only valid data but also invalid data and data of a global input/output line is required.